High-voltage discrete and integrated circuit devices, which are currently employed in a wide variety of electrical and electronic circuit architectures, are subject to excessive electric field intensity created in the vicinity of a reverse-biased PN junction. One particularly effective mechanism to deal with this problem has been to use a junction termination extension (JTE), as a barrier against the effects of the electric field. In a typical architecture, the JTE device is passivated by a relatively thick bulk oxide layer that is formed by the process sequence shown in FIG. 1, respective steps of which yield a device structure shown in the associated cross-sectional diagrams of FIGS. 2A-2F.
More particularly, as shown at step 101, the conventional process begins by exposing the top surface of a semiconductor (silicon) substrate 1, shown in FIG. 2A, to a `wet` or steam ambient, so as to rapidly grow a relatively thick ubiquitous oxide layer 2, that is to serve as part of the bulk JTE oxide. As shown at step 103 and FIG. 2B, the oxide layer 2 is then patterned, etched and cleaned/rinsed to open a plurality of implant apertures 3, which expose corresponding (JTE dopant-implant) surface portions 4 in the top surface of substrate 1.
In step 105, conductivity type determining impurities 5 are implanted through the implant apertures 3 of the oxide layer 2, forming a plurality of JTE surface regions shown at 6 in FIG. 2C. This implant step introduces unwanted near-surface pockets of crystalline damage 7 in the vicinity of the top surface of the silicon substrate. In order to remove this crystalline damage and prevent stacking fault formation, at step 107, a wet or stream screen oxide layer 8 is rapidly grown directly on the JTE surface regions 6, as shown in FIG. 2D. Unfortunately, because the oxide layer 8 is grown rapidly and directly upon the implanted surface of the silicon, it is of relatively poor quality, and can be expected to negatively impact the quality of any subsequently formed oxide.
Following formation of the screen oxide layer 8, the device is subjected to a dopant drive-in step 109, which causes the dopant of the implanted regions 6 to diffuse into the surrounding substrate, and essentially define the JTE structure, as shown at 6' in FIG. 2E. Although some additional dopant diffusion will occur during subsequent oxidation,.the bulk of the dopant drive-in is completed in this step. The JTE oxide process is completed by performing a further rapid steam or wet oxidation step 111, which fills in the implant apertures 3 with oxide 9 and results in the JTE structure shown in FIG. 2F.
Because each of the oxide layers formed in the process of FIGS. 1 and 2, particularly those overlying the implanted regions, are grown rapidly in a wet or stream atmosphere, they are of relatively low density. As a result they facilitate segregation or out-diffusion of dopants into the oxide, and reduce the quality of any oxide grown thereon. This has the unwanted effect of allowing the total oxide charge (Qox) and Sio.sub.2 --Si interface trap density (Dit) to increase, which degrades high voltage stability.